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? 1996 mos integrated circuit MC-42S4LFG64S 3.3 v operation 4m-word by 64-bit dynamic ram module (so dimm), edo data sheet the mark ? ? shows major revised points. document no. m12087ej3v0ds00 (3rd edition) date published octocer 1997 ns printed in japan the information in this document is subject to change without notice. description the MC-42S4LFG64S is a 4,194,304 words by 64 bits dynamic ram module (small outline dimm) on which 4 pieces of 64m dram : m pd42s65165 are assembled. this module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features ? edo (hyper page mode) ? 4,194,304 words by 64 bits organization ? fast access and cycle time family access time r/w c y cle time edo (h y per pa g e mode) power consumption (max.) (max.) (min.) cycle time (min.) active standby MC-42S4LFG64S-a50 50 ns 84 ns 20 ns 2.16 w 2.88 mw MC-42S4LFG64S-a60 60 ns 104 ns 25 ns 1.87 w (cmos level input) ? refresh cycle family refresh cycle refresh MC-42S4LFG64S-a50 4,096 cycles / 128 ms /ras only refresh, normal read / write, /cas before /ras refresh, MC-42S4LFG64S-a60 /cas before /ras self refresh, hidden refresh ? 144-pin small outline dual in-line memory module (pin pitch = 0.8 mm) ? single +3.3 v 0.3 v power supply ? serial pd ordering information part number access time (max.) package mounted devices MC-42S4LFG64Sa-a50 50 ns 144-pin small outline dimm (socket type) 4 pieces of m pd42s65165g5 (400 mil tsop(ii)) MC-42S4LFG64Sa-a60 60 ns edge connector : gold plated [double side]
2 MC-42S4LFG64S pin configuration 144-pin dual in-line memory module socket type (edge connector: gold plated) [ MC-42S4LFG64Sa ] a0 - a11 : address inputs [ row : a0 - a11, column : a0 - a9 ] dq0 - dq63 : data inputs / outputs / ras0 : row address strobe / cas0 - /cas7 : column address strobe / we : write enable / oe : output enable sda : serial data i/o for pd scl : clock input for pd v cc : power supply gnd : ground nc : no connection 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 gnd dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 gnd /cas0 /cas1 a0 a1 a2 gnd dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 gnd nc nc 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 nc nc /we /ras0 nc /oe gnd nc nc dq 16 dq 17 dq 18 dq 19 gnd dq 20 dq 21 dq 22 dq 23 a6 a8 gnd a9 a10 /cas2 /cas3 gnd dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 gnd sda 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 gnd dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 gnd /cas4 /cas5 a3 a4 a5 gnd dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 gnd nc nc 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 nc nc nc nc nc nc gnd nc nc dq 48 dq 49 dq 50 dq 51 gnd dq 52 dq 53 dq 54 dq 55 a7 a11 gnd nc nc /cas6 /cas7 gnd dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 gnd scl cc cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v / xxx indicates active low si gnal.
3 MC-42S4LFG64S block diagram remark d0 - d3 : m pd42s65165 (4m words by 16 bits organization) /ras0 /we /oe /cas0 /cas1 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 /lcas dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 /ucas dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 /ras /we /oe /cas2 /cas3 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 /lcas dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 /ucas dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 /ras/we /oe d0 d1 /cas4 /cas5 dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 i/o 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 /lcas dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 /ucas dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 /ras /we /oe /cas6 /cas7 dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 /lcas dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 /ucas dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 /ras /we /oe d2 d3 a0 - a11 a0 - a11 : d0 - d3 v cc d0 - d3 gnd d0 - d3 serial pd scl sda a0 a1 a2
4 MC-42S4LFG64S electrical specifications ? all voltages are referenced to gnd. ? after power up (v cc 3 v cc (min.) ), wait more than 100 m s (/ras, /cas inactive) and then, execute eight /cas before /ras or /ras only refresh cycles as dummy cycles to initialize internal circuit. absolute maximum ratings parameter symbol condition rating unit voltage on any pin relative to gnd v t - 0.5 to +4.6 v supply voltage v cc - 0.5 to +4.6 v output current i o 50 ma power dissipation p d 4w operating ambient temperature t a 0 to +70 c storage temperature t stg - 55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il - 0.3 +0.8 v operating ambient temperature t a 070 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a11 50 pf c i2 /ras0 55 c i3 /cas0 - /cas7 30 c i4 /we 55 c i5 /oe 55 data input/output capacitance c i/o dq0 - dq63 30 pf
5 MC-42S4LFG64S dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes operating current i cc1 /ras, /cas cycling t rac = 50 ns 600 ma 1, 2, 3 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 520 standby current i cc2 /ras, /cas 3 v ih (min.) , i o = 0 ma 4.0 ma /ras, /cas 3 v cc - 0.2 v, i o = 0 ma 0.8 /ras only refresh current i cc3 /ras cycling, /cas 3 v ih (min.) t rac = 50 ns 600 ma 1, 2, 3 ,4 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 520 operating current i cc4 /ras v il (max.) , /cas cycling t rac = 50 ns 480 ma 1, 2, 5 (hyper page mode (edo)) t hpc = t hpc (min.) , i o = 0 ma t rac = 60 ns 400 /cas before /ras i cc5 /ras cycling t rac = 50 ns 600 ma 1, 2 refresh current t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 520 /cas before /ras i cc6 /cas before /ras refresh : t ras 300 ns 2.0 ma 1, 2 long refresh current t rc = 31.3 m s (4,096 cycles / 128 ms) /ras, /cas : v cc - 0.2 v v ih v ih (max.) 0 v v il 0.2 v standby : t ras 1 m s 2.4 ma 1, 2 /ras, /cas 3 v cc - 0.2 v address : v ih or v il /we, /oe : v ih i o = 0 ma /cas before /ras i cc7 /ras, /cas : 1.6 ma 2 self refresh current t rass = 5 ms v cc - 0.2 v v ih v ih (max.) 0 v v il 0.2 v i o = 0 ma input leakage current i i (l) v i = 0 to 3.6 v - 20 +20 m a all other pins not under test = 0 v output leakage current i o (l) v o = 0 to 3.6 v - 5+5 m a output is disabled (hi - z) high level output voltage v oh i o = - 2.0 ma 2.4 v low level output voltage v ol i o = +2.0 ma 0.4 v notes 1. i cc1 , i cc3 , i cc4 , i cc5 and i cc6 depend on cycle rates (t rc and t hpc ). 2. specified values are obtained with outputs unloaded. 3. i cc1 and i cc3 are measured assuming that address can be changed once or less during /ras v il (max.) and /cas 3 v ih (min.) . 4. i cc3 is measured assuming that all column address inputs are held at either high or low. 5. i cc4 is measured assuming that all column address inputs are switched only once during each hyper page (edo) cycle.
6 MC-42S4LFG64S ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions (1) input timing specification (2) output timing specification (3) output load condition v il (max.) = 0.8 v v ih (min.) = 2.0 v v oh (min.) = 2.0 v v ol (max.) = 0.8 v t t = 2 ns t t = 2 ns i/o 870 100 pf 1,180 v cc c l
7 MC-42S4LFG64S common to read, write, read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t rc 84 - 104 - ns /ras precharge time t rp 30 - 40 - ns /cas precharge time t cpn 7 - 10 - ns /ras pulse width t ras 50 10,000 60 10,000 ns 1 /cas pulse width t cas 8 10,000 10 10,000 ns /ras hold time t rsh 13 - 15 - ns /cas hold time t csh 38 - 40 - ns /ras to /cas delay time t rcd 11 37 14 45 ns 2 /ras to column address delay time t rad 9251230 ns 2 /cas to /ras precharge time t crp 5 - 5 - ns 3 row address setup time t asr 0 - 0 - ns row address hold time t rah 7 - 10 - ns column address setup time t asc 0 - 0 - ns column address hold time t cah 7 - 10 - ns /oe lead time referenced to /ras t oes 0 - 0 - ns /cas to data setup time t clz 0 - 0 - ns /oe to data setup time t olz 0 - 0 - ns /oe to data delay time t oed 10 - 13 - ns transition time (rise and fall) t t 150150 ns refresh time t ref - 128 - 128 ms notes 1. in /cas before /ras refresh cycles, t ras (max.) is 100 m s. if 10 m s < t ras < 100 m s, /ras precharge time for /cas before /ras self refresh (t rps ) is applied. 2. for read cycles, access time is defined as follows: input conditions access time access time from /ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 3. t crp (min.) requirement is applied to /ras, /cas cycles.
8 MC-42S4LFG64S read cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. access time from /ras t rac - 50 - 60 ns 1 access time from /cas t cac - 15 - 15 ns 1 access time from column address t aa - 25 - 30 ns 1 access time from /oe t oea - 13 - 15 ns column address lead time referenced to /ras t ral 25 - 30 - ns read command setup time t rcs 0 - 0 - ns read command hold time referenced to /ras t rrh 0 - 0 - ns 2 read command hold time referenced to /cas t rch 0 - 0 - ns 2 output buffer turn-off delay time from /oe t oez 010013 ns 3 /cas hold time to /oe t cho 5 - 5 - ns 4 notes 1. for read cycles, access time is defined as follows: input conditions access time access time from /ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 2. either t rch (min.) or t rrh (min.) should be met in read cycles. 3. t oez (max.) defines the time when the output achieves the condition of hi-z and is not referenced to v oh or v ol . 4. /we : inactive (in read cycle) /cas : inactive, /oe : active ...... t cho is effective. /ras, /oe : active ...... t och is effective.
9 MC-42S4LFG64S write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. /we hold time referenced to /cas t wch 7 - 10 - ns 1 /we pulse width t wp 7 - 10 - ns 1 /we lead time referenced to /ras t rwl 13 - 15 - ns /we lead time referenced to /cas t cwl 7 - 10 - ns /we setup time t wcs 0 - 0 - ns 2 /oe hold time t oeh 0 - 0 - ns data-in setup time t ds 0 - 0 - ns 3 data-in hold time t dh 7 - 10 - ns 3 notes 1. t wp (min.) is applied to late write cycles or read modify write cycles. in early write cycles, t wch (min.) should be met. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. 3. t ds (min.) and t dh (min.) are referenced to the /cas falling edge in early write cycles. in late write cycles and read modify write cycles, they are referenced to the /we falling edge. read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. read modify write cycle time t rwc 107 - 133 - ns /ras to /we delay time t rwd 64 - 77 - ns 1 /cas to /we delay time t cwd 27 - 32 - ns 1 column address to /we delay time t awd 39 - 47 - ns 1 note 1. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate.
10 MC-42S4LFG64S hyper page mode (edo) parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t hpc 20 - 25 - ns 1 /ras pulse width t rasp 50 125,000 60 125,000 ns /cas pulse width t hcas 8 10,000 10 10,000 ns /cas precharge time t cp 7 - 10 - ns access time from /cas precharge t acp - 30 - 35 ns /cas precharge to /we delay time t cpwd 41 - 52 - ns 2 /ras hold time from /cas precharge t rhcp 30 - 35 - ns read modify write cycle time t hprwc 52 - 66 - ns data output hold time t dhc 5 - 5 - ns /oe to /cas hold time t och 5 - 5 - ns 3 /oe precharge time t oep 5 - 5 - ns output buffer turn-off delay from /we t wez 010013 ns 4,5 /we pulse width t wpz 7 - 10 - ns 5 output buffer turn-off delay from /ras t ofr 010013 ns 4,5 output buffer turn-off delay from /cas t ofc 010013 ns 4,5 notes 1. t hpc (min.) is applied to /cas access. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate. 3. /we : inactive (in read cycle) /cas : inactive, /oe : active ...... t cho is effective. /cas, /oe : active ...... t och is effective. 4. t ofc (max.) , t ofr (max.) and t wez (max.) define the time when the output achieves the conditions of hi-z and is not referenced to v oh or v ol . 5. to make dqs to hi-z in read cycle, it is necessary to control /ras, /cas, /we, /oe as follows. the effective specification depends on state of each signal. (1) both /ras and /cas are inactive (at the end of the read cycle) /we : inactive, /oe : active t ofc is effective when /ras is inactivated before /cas is inactivated. t ofr is effective when /cas is inactivated before /ras is inactivated. the slower of t ofc and t ofr becomes effective. (2) both /ras and /cas are active or either /ras or /cas is active (in read cycle) /we, /oe : inactive ...... t oez is effective. both /ras and /cas are inactive or /ras is active and /cas is inactive (at the end of read cycle) /we, /oe : active and either t rrh or t rch must be met ...... t wez and t wpz are effective. the faster of t oez and t wez becomes effective. the faster of (1) and (2) becomes effective.
11 MC-42S4LFG64S refresh cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. /cas setup time t csr 5 - 5 - ns /cas hold time (/cas before /ras refresh) t chr 10 - 10 - ns /ras precharge /cas hold time t rpc 5 - 5 - ns /ras pulse width (/cas before /ras self refresh) t rass 100 - 100 - ns /ras precharge time (/cas before /ras self refresh) t rps 90 - 110 - ns /cas hold time (/cas before /ras self refresh) t chs - 50 -- 50 - ns /we setup time t wsr 10 - 10 - ns /we hold time t whr 15 - 15 - ns
12 MC-42S4LFG64S serial pd byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 number of serial pd bytes 5dh 0 1 0 1 1 1 0 1 93 bytes 1 serial memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 02h 0 0 0 0 0 0 1 0 edo 3 number of rows 0ch 0 0 0 0 1 1 0 0 12 rows 4 number of columns 0ah 0 0 0 0 1 0 1 0 10 columns 5 number of banks 01h 0 0 0 0 0 0 0 1 1 bank 6 data width 40h 0 1 0 0 0 0 0 0 64 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 01h 0 0 0 0 0 0 0 1 lvttl 9 /ras access time -a50 32h 0 0 1 1 0 0 1 0 50 ns -a60 3ch 0 0 1 1 1 1 0 0 60 ns 10 /cas access time -a50 0fh 0 0 0 0 1 1 1 1 15 ns -a60 0fh 0 0 0 0 1 1 1 1 15 ns 11 error detection/correction 00h 0 0 0 0 0 0 0 0 none 12 refresh period 83h 1 0 0 0 0 0 1 1 self refresh (31.3 m s) 13dram width 10h00010000 16 14 error checking dram width 00h 0 0 0 0 0 0 0 0 none 15 - 61 00h 0 0 0 0 0 0 0 0 62spd revision 01h000000011 63 checksum for bytes 0-62 -a50 94h 1 0 0 1 0 1 0 0 -a609eh10011110 64 manufactures jedec id code per jep-106e 10h00010000 65-71 00h 0 0 0 0 0 0 0 0 72 manufacturing location 73 part name 34h 0 0 1 1 0 1 0 0 74 part name 32h 0 0 1 1 0 0 1 0 75 part name 53h 0 1 0 1 0 0 1 1 76 part name 34h 0 0 1 1 0 1 0 0 77part name 4ch01001100 78 part name 46h 0 1 0 0 0 1 1 0 79 part name 47h 0 1 0 0 0 1 1 1 80 part name 36h 0 0 1 1 0 1 1 0 81 part name 34h 0 0 1 1 0 1 0 0 82 part name 53h 0 1 0 1 0 0 1 1 83 part name 41h 0 1 0 0 0 0 0 1 84part name 2dh00101101 85 part name 41h 0 1 0 0 0 0 0 1 86 part name -a50 35h 0 0 1 1 0 1 0 1 -a6036h00110110 87 part name 30h 0 0 1 1 0 0 0 0 88 part name 20h 0 0 1 0 0 0 0 0 89 part name 20h 0 0 1 0 0 0 0 0 90 part name 20h 0 0 1 0 0 0 0 0 91 pcb revision code 31h 0 0 1 1 0 0 0 1 92 blank 20h 0 0 1 0 0 0 0 0 remark 1 : high level (serial data), 0 : low level (serial data)
13 MC-42S4LFG64S read cycle data out hi - z v ih v il /cas v ih v il /ras v ih v il address v ih v il /we v oh v ol dq v ih v il /oe crp t rcd t csh t ras t rc t rsh t cas t ral t cah t asc t col. rcs t och t oes t oea t clz t olz t cac t aa t rac t rp t cpn t rch t rrh t wpz t cho t wez t ofc t oez t ofr t hi - z asr t rah t rad t row
14 MC-42S4LFG64S early write cycle ds t crp t rcd t wch t wcs t asr t rah t rad t asc t cah t cas t rsh t csh t ras t rp t rc t v ih v il v ih v il v ih v il v ih v il v ih v il /ras address /we row col. data in dh t cpn t /cas dq remark /oe : dont care
15 MC-42S4LFG64S late write cycle /ras address /we row col. data in /oe hi - z rc t rp t ras t crp t rcd t cas t rsh t csh t cpn t asr t rah t rad t asc t cah t wp t rwl t cwl t rcs t oeh t oed t ds t dh t v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il /cas dq
16 MC-42S4LFG64S read modify write cycle /ras /cas address /we dq /oe dq row col. data in hi - z data out hi - z v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il rwc t ras t rp t cpn t rsh t cas t csh t rcd t crp t asr t rah t rad t cah t asc t rcs t oea t oeh t ds t dh t oed t aa t rac t cac t clz t olz t oez t cwl t rwl t wp t rwd t awd t cwd t
17 MC-42S4LFG64S hyper page mode (edo) read cycle /ras /cas address /we /oe dq t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t rad t cah t asc t cah t asc t cah t ral t rcs t rch t rrh t wpz t wez t oez t acp t aa t cac t acp t aa t cac t dhc t dhc t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z t ofr t ofc t och v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il cho t t asc remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
18 MC-42S4LFG64S hyper page mode (edo) read cycle (/we control) /ras /cas address /we /oe t rasp t rp t crp t rcd t hcas t csh t rhcp t rsh t hcas t cpn t hcas t asr t rah t rad t cah t asc t cah t asc t cah t ral t rrh t wpz t ofr t ofc t oez t aa t aa t clz t cac t cac t clz t wez t wez t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z dq t rch t wpz t rcs t rch t wpz t rcs t rch hi - z hi - z t wez t och v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il cho t t asc t rcs remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
19 MC-42S4LFG64S hyper page mode (edo) read cycle (/oe control) hi - z hi - z row col.a col.b col.c /ras /cas address /oe dq data out a data out c /we v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il rasp t rp t rhcp t cpn t rsh t hcas t cp t hpc t hcas t cp t hcas t csh t rcd t crp t rad t rah t asr t asc t cah t cah t asc t cah t ral t ofr t ofc t rrh t rch t oes t aa t cac t cac t aa t rac t rcs t oep t t och t oea t cho t acp t och t oep t cho t oep t aa t cac t acp t och t cho t oez t oea t t olz t oez t oea t olz t oez t clz t oez t clz t olz t data out b data out b asc t remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
20 MC-42S4LFG64S hyper page mode (edo) early write cycle data in v ih v il v ih v il /we v ih v il address v ih v il v ih v il /ras crp t rad t asr t rah t asc t cah t asc t cah t wch t wcs t wch t dh t ds t ds t dh t data in data in ds t dh t wch t row col. col. col. asc t cah t cpn t rp t ral t hcas t cp t hcas t hpc t rsh t rhcp t rasp t cp t hcas t rcd t csh t wcs t wcs t /cas dq remarks 1. /oe : dont care 2. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
21 MC-42S4LFG64S hyper page mode (edo) late write cycle /ras address /we col. col. col. row hi-z hi-z hi-z data in data in data in /oe rasp t rhcp t rp t cpn t rsh t hcas t hcas t hpc t cp t cp t csh t hcas t rcd t crp t asr t rah t rad t cah t cah t asc t ral t cah t wp t rwl t cwl t rcs t wp t cwl t wp t rcs t cwl t rcs t oeh t oeh t oeh t oed t ds t dh t oed t ds t dh t oed t ds t dh t v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il asc t asc t /cas dq remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
22 MC-42S4LFG64S hyper page mode (edo) read modify write cycle t rcs /cas t cpn t cp t hcas t hcas t cp t hprwc t hcas t rcd /ras t rasp t rp t crp address t asr t rah t rad t asc t cah t asc t cah t cah t asc row col. col. col. t ral /we t rwd t olz t dh t ds t awd t cwd t wp t rcs t cwl t acp t cpwd t awd t cwd t wp t cwl t acp t cpwd t awd t cwd t rcs t cwl t rwl t wp /oe dq out t clz t oed t oea t cac t aa t rac in t oea t oeh t cac t aa t olz t dh t ds out t oez t oed in t olz t dh t ds out t oez t clz t oed in t oeh t aa t cac t oea t oeh hi-z hi-z hi-z hi-z dq v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t oez t clz remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
23 MC-42S4LFG64S hyper page mode (edo) read and write cycle t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t rad t cah t asc t cah t asc t cah t ral t rcs t rch t acp t aa t cac t wez t dhc t oea t rac t aa t cac t clz row col. col. col. data out data out hi - z t wcs t wch hi - z t dh t ds data in t och t olz cho t /ras v ih v il v ih v il address v ih v il /we v ih v il /oe v ih v il v oh v ol v ih v il t asc t oez /cas dq dq remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
24 MC-42S4LFG64S /cas before /ras self refresh cycle remark address, /oe : don't care dq : hi-z cautions on use of /cas before /ras self refresh /cas before /ras self refresh can be used independently when used in combination with distributed /cas before /ras long refresh; however, when used in combination with burst /cas before /ras long refresh or with long /ras only refresh (both distributed and burst), the following cautions must be observed. (1) normal combined use of /cas before /ras self refresh and burst /cas before /ras long refresh when /cas before /ras self refresh and burst /cas before /ras long refresh are used in combination, please perform /cas before /ras refresh 4,096 times within a 64 ms interval just before and after setting /cas before /ras self refresh. (2) normal combined use of /cas before /ras self refresh and long /ras only refresh when /cas before /ras self refresh and /ras only refresh are used in combination, please perform /ras only refresh 4,096 times within a 64 ms interval just before and after setting /cas before /ras self refresh. (3) if t rass(min.) is not satisfied at the beginning of /cas before /ras self refresh cycles (t ras < 100 m s), /cas before /ras refresh cycles will be executed one time. if 10 m s < t ras < 100 m s, /ras precharge time for /cas before /ras self refresh (t rps ) is applied. and refresh cycles (4,096 / 128 ms) should be met. for details, please refer to how to use dram users manual. t csr t wsr t whr t rass t rps t chs t cpn t rpc t crp /ras v ih v il /cas v ih v il /we v ih v il
25 MC-42S4LFG64S /cas before /ras refresh cycle t t t t t t t t t t t t t t t t csr chr wsr whr rc rp rpc csr chr ras ras rp rc rpc cpn crp /ras v ih v il v ih v il /we v ih v il t t wsr whr /cas /ras remark address, /oe : don't care dq : hi-z /ras only refresh cycle row row t rc t rc t ras t ras t rp t rp t crp t rpc t cpn t asr t asr t rah t rah t crp v ih v il /ras v ih v il v ih v il address /cas remark /we, /oe : don't care dq : hi-z
26 MC-42S4LFG64S hidden refresh cycle (read) tt t tt t row col. data out hi - z hi - z t t t t t t t t t t t t t t t t t t t t t t rc rc ras ras rp crp t rcd rsh chr cpn t asr rad rah ral cah asc rch whr wpz wez cho ofc ofr oez rcs t oes t oea rac aa cac olz clz /ras v ih v il v ih v il address v ih v il /we v ih v il /oe v ih v il v oh v ol rp t /cas dq
27 MC-42S4LFG64S hidden refresh cycle (write) t t t t t t t t t t row col. t t t t t t t t data in rc ras rp rc ras rcd rsh chr cpn cah asc rad rah asr crp wcs t wch ds dh /ras v ih v il v ih v il address v ih v il /we v ih v il v ih v il rp t /cas dq t whr t wsr remark /oe : dont care
28 MC-42S4LFG64S package drawing [ MC-42S4LFG64Sa ] 144 pin dual in-line module (soket type) item millimeters inches b a d 4.6 0.181 x 2.55 min. 0.100 min. c 29.0 1.142 u 3.2 min. 0.125 min. d1 1.50.1 0.0590.004 y 2.0 min. 0.078 min. 67.6 2.661 23.2 0.913 a1 67.60.15 2.661 e j 3.3 0.13 h 0.8 (t.p.) 0.031 (t.p.) l 20.0 0.787 m 25.40.15 1.00.006 32.8 1.291 n q r2.0 r0.079 3.8 max. 0.15 max. r 4.00.10 0.157 +0.005 C0.004 s t 1.00.1 0.039 +0.005 C0.004 1.8 f 0.071 f d2 4.0 0.157 +0.005 C0.004 +0.007 C0.006 y r j h a d q t u detail of a part d2 d1 x v (optional holes) s w n a m1 (area a) m2 (area b) l z a1 e c b m m1 3.4 1.315 m2 22.0 0.866 w 0.60.05 0.024 +0.002 C0.003 v 0.25 max. 0.01 max. m144s-80a5 z 2.0 min. 0.078 min. h
29 MC-42S4LFG64S [ memo ]
30 MC-42S4LFG64S [ memo ]
31 MC-42S4LFG64S 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme-diately after power-on for devices having reset function. notes for cmos devices
MC-42S4LFG64S [memo] caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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